1. Field of the Invention
The invention relates generally to integrated circuit fabrication and, more particularly, to methods for conversion of an integrated circuit pattern into mask sets that optimize fabrication of said integrated circuit through an edge based pattern transfer process.
2. Description of the Related Art
The integrated circuit (“IC”) industry strives for electronic devices that are both faster and infinitely smaller. Accordingly, the IC industry is driven by a demand for methods of fabricating IC features with improved dimensional control. IC fabrication with improved dimensional control creates ever smaller IC features, which in turn increases the circuit density of the IC. Increased circuit density yields higher chip performance. Therefore, a substantial economic advantage can be gained through the development of improved methods of fabricating IC features with improved dimensional control. Two prior art IC fabrication methods include optical lithography and sidewall image transfer (“SIT”).
Optical lithography, one prior art IC fabrication method, comprises a patterning operation that sequentially modifies a semiconductor substrate and various films deposited on such substrate through the use of a light source. A layer of light sensitive polymer film, e.g. photoresist or resist, is coated onto the substrate followed by exposing the resist to the light source through a master stencil, i.e. photomask or mask. The mask includes patterned IC features, such as lines and spaces, that are transferred to the resist. After the resist is exposed, the optical lithography tool immerses the resist in solvent. The solvent defines the features that were transferred to the resist.
The prior art method of optical lithography is problematic because optical lithography tools are limited by the light source's wavelength. As IC features shrink to, for example, line widths of 45.0 nm, the inability of optical lithography to fabricate IC features with such diminutive line widths becomes increasingly problematic. In addition to fabricating infinitely smaller IC features, optical lithography must have the capability of creating IC features with increasing dimensional control. For example, the gate of a field effect transistor, one such feature fabricated through optical lithography, must be controlled to better than +/−10% of its nominal width. Diffraction effects, however, limit optical lithography's ability to deliver such dimensionally controlled IC features. The accuracy with which optical lithography renders IC features is inversely proportional to the resolution of the IC features being transferred. The IC features produced by optical lithography are limited to line widths greater than the minimum resolution of the optical lithography tool, which is ultimately limited by the wavelength (“λ”) of the light source used by the optical lithography tool to expose the resist. For at least these reasons, optical lithography is deficient.
SIT, another prior art IC fabrication method, and further an edge based image transfer process, comprises depositing an etch-masking medium, e.g. nitride, on the sidewalls of a mesa, and removing the mesa, which leaves behind sidewall structures. The sidewall structures act as the primary image transfer medium for the patterning of narrow IC features.
While SIT has improved dimensional control over the prior art method of optical lithography, the prior art method SIT is problematic because only one IC feature size can be fabricated per SIT operation, only closed loop topographies can be created, and SIT has an incomprehensive IC feature shape library, in other words, only certain IC feature shapes can be fabricated with SIT. While dimensional control is important, sometime dimensional control is secondary to other considerations, e.g. larger feature size, chip performance, and cost. With SIT, if such other considerations become of primary importance, the IC designer must resort from SIT to optical lithography to create the desired IC feature. In addition to these considerations, SIT is disadvantageous because only a limited number of shapes, and more specifically closed loop shapes, can be created by SIT. The IC designer must resort from SIT to optical lithography whenever a shape must be fabricated that SIT cannot fabricate. Another reason that SIT is problematic is the challenge associated with the translation of the IC layout to the mask set required to exercise edge based imaging process. In sum, while SIT improves upon dimensional control, SIT does not entirely eliminate reliance on optical lithography. For at least these reasons, SIT alone is deficient. It should be noted that while SIT is an edge based image transfer process, alternating phase shift is another edge based image transfer process with the similar benefits and deficiencies of SIT.
What is needed in the art is an improved method for fabrication of integrated circuit that creates a final mask set that optimizes the use of an edge based image transfer mask based upon considerations such as dimensional control, chip performance, and cost and compensates for any deficiencies in creation of the integrated circuit with block and optical lithography masks.